The implementation of wireless transceivers on a single chip in a single technology requires digital realizations of traditional analog building blocks such as phaselocked loops (PLLs). Alldigital PLLs (ADPLLs) utilize the zero crossings of signals instead of their amplitudes to realize the frequency synthesizer entirely in digital CMOS technology. This thesis analyzes ADPLLs and highlights the systemlevel signal processing aspects. A zdomain model and a mixedsignal model are used to develop signal processing algorithms, to perform highlevel simulations, and to evaluate the performance of ADPLLs. The impact of imperfections on the output phase noise spectrum are analytically described and compared to eventdriven simulation outcomes. Oscillator noise, frequency quantization noise with SigmaDelta noise shaping, and reference clock jitter raise the output phase noise level, whereas phase quantization and injection pulling manifest themselves as spurs in the output phase noise spectrum. Furthermore, the behavior of a wellknown phasedomain ADPLL architecture that employs a periodically timevarying system clock to synchronize the oscillator output clock and the reference clock is extensively investigated and mathematically described. Based on the analysis of injection pulling spurs and the analysis of the timevarying ADPLL operation, an alternative ADPLL architecture, that directly utilizes the uniform reference clock as system clock, is proposed. The advantages are a reduced complexity of the circuits and an improved performance concerning spurs in the phase noise spectrum. Finally, a fast frequencyhopping ADPLL is proposed that enables frequency hops within less than one reference cycle with a frequency resolution of less than 20 ppm of the synthesized frequency. The proposed ADPLL is suitable for Multiband OrthogonalFrequencyDivisionMultiplexing UltraWideband (MBOFDMUWB) communication systems, where the time between the recurrence of a frequency band is short and the requirements on the phase noise are not demanding. 
