Modeling and Simulation of Error Correction Encoding for Networks-on-Chip

Project Type: Master/Diploma Thesis
Student: Lauter Robert
Mentor: Gernot Kubin


 Networks-on-Chip (NoC) are an arising technique to master the inadequacies when connecting the components of complex Systems-on-Chip (SoC) via traditional bus systems. This approach recovers the sharp advantage on time-to-market constraints of simple SoC. When NoC is available as a template, the communication infrastructure does not need to be custom tailored. For this reason NoC are of active current research interest. Power consumption of the network has been identified as one of the hardest challenges for their universal application and this thesis focuses on reducing power consumption on the transmission lines connecting neighboring network nodes. A new approach of power reduction by aggressive voltage reduction on this transmission lines is analyzed. The resulting sensitivity on transmission faults is compensated by the application of efficient parallel BCH (Bose-Ray-Chaudhuri-Hocquenghem) error correcting codes. The working on this topic,has shown that the furtherparameters of the NoC are of dominant influence on the success of this method. Hence an existing simulation concept was widely expanded and extended to a full blown generic NoC simulator. This layered simulator realizes a homogeneous, closed or open, packet switched mesh structure. Special virtual circuit links work as a measure to obtain additionally the advantages of circuit switched networks. Error correction is carried out either on link layer or on network layer and the use of error detection is permitted by performing automatic resend requests. Special attention has been dedicated to programming and description of a highly variable BCH code unit, furthermore to the description of power models for the logic blocks of this unit and the transmission lines. A model relating the total communication error probability, resulting from voltage reduction, is also described in detail. A representative example (MPEG4 encoder) was realized in order to proof the applicability of the concept, the simulator and the different models. Different network related effects and the potential of power reduction by applying BCH codes are demonstrated.