Magnitude Response Mismatch Compensation in Time-interleaved Analog-to-Digital Converters

Project Type: Master/Diploma Thesis
Student: Mendel Stefan
Mentor: Gernot Kubin


 In order to comply with modern telecommunication standards, a high-speed and high-resolution analog-to-digital conversion is needed. One way to increase the sample rate beyond its production limits is to exploit parallelism, e.g., in a time-interleaved manner. For this purpose several channel analog-to-digital converters (ADCs) are operated in parallel with the same sampling rate but with phase shifts to built a time-interleaved ADC. As a result, the sample rate is increased by the number of channels. Unfortunately, the channel ADCs are not identical and due to fabrication imperfections additional mismatch effects decrease the performance. This thesis analyses the channel mismatches, namely offset, static gain, timing, frequency response, and nonlinearity mismatches in detail. In addition, a novel description of a time-interlaved ADC, including nonlinearity mismatches modeled by Volterra series expansion, is derived. The main contribution of this thesis is a novel magnitude response mismatch compensation method. First, the method is derived for a two-channel time-interleaved ADC. In a second step the concept is generalized to an arbitrary number of channels. Various simulations confirm the effectiveness of the proposed method for narrow-band and wide-band signals.