Reconfigurable logic (FPGA) allows to implement custom-precision arithmetic units. In this work we propose an algorithm, which employs a Bayesian technique to determine the optimal amount of bits for representing the involved continuous variables. We restrict ourselves to the problem of nonlinear approximation, where an assumed data model consists of superimposed signals with unknown parameters. By fitting such models using a variational Bayesian EM-based algorithm, we can determine the importance of each signal component using a techniques inspired by the Bayesian evidence procedure. Due to the structure of the obtained variational update expressions, it becomes possible to show that the evidence value represents the combined effect of the relevance of a signal component for explaining the measurement data, and additive noise, associated with this component. This insight allows to interpret the value of the evidence parameters in terms of a Signal-to-Noise ratio, which is then used to develop an optimal discretization scheme. The effectiveness of the proposed approach is demonstrated with two synthetic examples, showing a bitwidth reduction of more than 70\% at the cost of a relative mean squared error of 0.0036 and 0.012, respectively.

}, isbn = {978-1-4244-4295-9}, doi = {10.1109/ICASSP.2010.5495115}, url = {http://dx.doi.org/10.1109/ICASSP.2010.5495115}, author = {Dmitriy Shutin and Manfred M{\"u}cke} }